Sequential equivalence techniques for high performance design

Quite often in semiconductor industry, when a product is nearing its launch date, most of us have had the deja-vu situation of performance to time-to-market trade-offs; especially in high-performance designs. Sequential equivalence checking opens up possibilities in this area, by enabling performanc...

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Bibliographic Details
Published in2007 7th International Conference on ASIC pp. 1162 - 1165
Main Author Balakrishnan, S.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2007
Subjects
Buildings
Computer bugs
Design engineering
Design methodology
Electronics industry
Sequential analysis
Testing
Time to market
Timing
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Summary:Quite often in semiconductor industry, when a product is nearing its launch date, most of us have had the deja-vu situation of performance to time-to-market trade-offs; especially in high-performance designs. Sequential equivalence checking opens up possibilities in this area, by enabling performance-tuning related sequential micro-architectural changes to be verified with significantly lower impact on effort estimates and risk. This nascent technology promises to change the way we look at eleventh hour changes.
ISBN:1424411319
9781424411313
ISSN:2162-7541
2162-755X
DOI:10.1109/ICASIC.2007.4415840