New 1.7kV IGBT chip with fine pattern and optimized buffer layer
Since the introduction of the IGBT, improvements in power loss and efficiency have been achieved by applying new technologies. In this paper, refinements in fine pattern processing technology and optimization of the low impurity profile of the buffer layer using thin wafer technology are proposed to...
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Published in | 2010 Twenty-Fifth Annual IEEE Applied Power Electronics Conference and Exposition (APEC) pp. 392 - 397 |
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Main Authors | , , , , , |
Format | Conference Proceeding |
Language | English |
Published |
IEEE
01.02.2010
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Subjects | |
Online Access | Get full text |
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Summary: | Since the introduction of the IGBT, improvements in power loss and efficiency have been achieved by applying new technologies. In this paper, refinements in fine pattern processing technology and optimization of the low impurity profile of the buffer layer using thin wafer technology are proposed to further reduce the power loss and improve efficiency in 1.7kV IGBT chips. |
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ISBN: | 9781424447824 1424447828 |
ISSN: | 1048-2334 2470-6647 |
DOI: | 10.1109/APEC.2010.5433642 |