New 1.7kV IGBT chip with fine pattern and optimized buffer layer

Since the introduction of the IGBT, improvements in power loss and efficiency have been achieved by applying new technologies. In this paper, refinements in fine pattern processing technology and optimization of the low impurity profile of the buffer layer using thin wafer technology are proposed to...

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Bibliographic Details
Published in2010 Twenty-Fifth Annual IEEE Applied Power Electronics Conference and Exposition (APEC) pp. 392 - 397
Main Authors Donlon, J.F., Motto, E.R., Satoh, K., Suzuki, K., Yoshihiura, Y., Takahashi, T.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.02.2010
Subjects
Buffer layers
Capacitance
Circuits
Doping profiles
Energy conservation
Impurities
Insulated gate bipolar transistors
Inverters
Motor drives
Ultra large scale integration
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Summary:Since the introduction of the IGBT, improvements in power loss and efficiency have been achieved by applying new technologies. In this paper, refinements in fine pattern processing technology and optimization of the low impurity profile of the buffer layer using thin wafer technology are proposed to further reduce the power loss and improve efficiency in 1.7kV IGBT chips.
ISBN:9781424447824
1424447828
ISSN:1048-2334
2470-6647
DOI:10.1109/APEC.2010.5433642