A novel method for ESD soft error analysis on integrated circuits using a TEM cell

The ultimate goal of this work is to predict ESD system level behavior. A methodology which can evaluate the IC immunity in terms of ESD-induced soft error is introduced. A modified TEM cell and a simple test board with a memory IC are designed for this purpose. The correlation between product level...

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Bibliographic Details
Published inElectrical Overstress / Electrostatic Discharge Symposium Proceedings 2012 pp. 1 - 6
Main Authors Jongsung Lee, Jaedeok Lim, Byongsu Seol, Zhen Li, Pommerenke, D.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2012
Subjects
Couplings
Electrostatic discharges
Generators
Integrated circuits
Noise
TEM cells
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Summary:The ultimate goal of this work is to predict ESD system level behavior. A methodology which can evaluate the IC immunity in terms of ESD-induced soft error is introduced. A modified TEM cell and a simple test board with a memory IC are designed for this purpose. The correlation between product level ESD standard test and the proposed IC immunity test is discussed.
ISBN:1467314676
9781467314671
ISSN:0739-5159
2164-9340