Late Breaking Results: Distributed Timing Analysis at Scale

As the design complexities continue to grow, the need to efficiently analyze circuit timing with billions of transistors is quickly becoming the major bottleneck to the overall chip design flow. In this work we introduce a distributed timer that (1) has scalable performance, (2) can be seamless inte...

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Bibliographic Details
Published in2019 56th ACM/IEEE Design Automation Conference (DAC) pp. 1 - 2
Main Authors Huang, Tsung-Wei, Lin, Chun-Xun, Wong, Martin D.F.
Format Conference Proceeding
LanguageEnglish
Published ACM 01.06.2019
Subjects
Benchmark testing
Industries
Logic gates
Pins
Runtime
Task analysis
Timing
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Summary:As the design complexities continue to grow, the need to efficiently analyze circuit timing with billions of transistors is quickly becoming the major bottleneck to the overall chip design flow. In this work we introduce a distributed timer that (1) has scalable performance, (2) can be seamless integrable to existing EDA applications, (3) enables transparent resource management, (4) has robust fault-tolerant control. We evaluate the distributed timer using a set of large industry benchmarks on a cluster with 24 nodes. The results show that the proposed timer achieves full accuracy over all designs with high performance and good scalability.
DOI:10.1145/3316781.3322470