Mapping Transaction Level Faults to Stuck-At Faults in Communication Hardware

Advances in semiconductor technology, the increasing complexity of digital systems and demand for faster time to market, have raised the level of design from transistor to Electronic System Level (ESL). However, digital system testing remains at lower levels of abstraction. To cover the gap between...

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Bibliographic Details
Published in2011 Asian Test Symposium pp. 114 - 119
Main Authors Javaheri, F., Namaki-Shoushtari, M., Kamranfar, P., Navabi, Z.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2011
Subjects
Automata
Data models
formal model
Hardware
high-level fault model
mutated model
Payloads
Protocols
synthesis
System recovery
test
Testing
TLM
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Summary:Advances in semiconductor technology, the increasing complexity of digital systems and demand for faster time to market, have raised the level of design from transistor to Electronic System Level (ESL). However, digital system testing remains at lower levels of abstraction. To cover the gap between system-level design and test, this paper presents a method of testing communication links at the ESL. For this purpose, system-level communication links are formally represented by Timed Automata (TA) to perform the fault simulation process automatically. This is facilitated by a set of high-level fault models that includes faults for data and control parts of a communication link. We show how the proposed high-level fault models map into faults at the gate level in communication hardware. The proposed test strategy not only applies communication links, but also can be used for testing processing elements using an appropriate fault model.
ISBN:9781457719844
1457719843
ISSN:1081-7735
2377-5386
DOI:10.1109/ATS.2011.94