A high-throughput low-latency arithmetic encoder design for HDTV

• Published in: 2013 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 998 - 1001
• Main Authors: Yuan Li, Shanghang Zhang, Huizhu Jia, Xiaodong Xie, Wen Gao
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2013
• Subjects: Bit rate; Context; Encoding; Random access memory; Real-time systems; Throughput; Video coding
• ISBN: 9781467357609; 146735760X
• ISSN: 0271-4302; 2158-1525
• DOI: 10.1109/ISCAS.2013.6572017

In this paper, we propose a high-throughput low-latency arithmetic encoder (AE) design suitable for high definition (HD) real-time applications employing advanced video coding standards such as H.264/AVC or AVS and using a macroblock (MB) level pipeline. First, in order to derive the performance requirement on the AE, a buffer model in connected with which it is designed is thoroughly analyzed. Then, using joint algorithm-architecture optimization and multi-bin processing techniques, we introduce a novel binary arithmetic coder (BAC) architecture with throughput of 2~4 bins per cycle sufficient for real-time encoding. Furthermore, a hybrid context memory scheme is presented to meet the throughput requirement on the BAC. Simulation result shows that our design can support 1080p at 60 fps for AVS HDTV real-time coding with a bin rate up to 107K per MB line. Synthesized with the TSMC 0.13μm technology, the AE can run at 200MHz and costs 47.3K gates. By operating at 130MHz, the design is also verified in an AVS HD encoder on a Xilinx Virtex-6 FPGA prototype board for 1080p at 30 fps.