A highly efficient pipeline architecture of RDO-based mode decision design for AVS HD video encoder

Like H.264, AVS video coding standard also uses macroblock (MB) based motion compensation (MC) and mode decision (MD). Rate distortion optimization (RDO) is the best known mode decision method, but with a high computational complexity that limits its applications. In our paper, firstly an MD algorit...

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Bibliographic Details
Published in2011 IEEE International Conference on Multimedia and Expo pp. 1 - 6
Main Authors Chuang Zhu, Yuan Li, Hui-zhu Jia, Xiao-dong Xie, Hai-bing Yin
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.07.2011
Subjects
AVS
Computational complexity
Discrete cosine transforms
Encoding
Hardware
mode decision
pipeline
Pipeline processing
Pipelines
RDO
Throughput
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Summary:Like H.264, AVS video coding standard also uses macroblock (MB) based motion compensation (MC) and mode decision (MD). Rate distortion optimization (RDO) is the best known mode decision method, but with a high computational complexity that limits its applications. In our paper, firstly an MD algorithm based on RDO is given, which makes more mode candidates enter into RDO mode decision with little hardware resource increment. We further analyze the pipeline structure in detail, and implement a block-level 5-stage hardware pipeline. It can support the real time RDO mode decision processing of 1080P@30fps, and the coding efficiency is about 0.5db higher than the traditional SAD method. Our design is described in high-level Verilog/VHDL hardware description language and implemented under SMIC 0.18-µm CMOS technology with 215K logic gates and 80 KB SRAMs.
ISBN:1612843484
9781612843483
ISSN:1945-7871
1945-788X
DOI:10.1109/ICME.2011.6011975