Large die size lead free flip chip ball grid array packaging considerations for 28nm fab technology

• Published in: 2012 IEEE 14th Electronics Packaging Technology Conference (EPTC) pp. 412 - 414
• Main Authors: Liao, J., Bachman, M., Osenbach, J.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2012
• Subjects: Bills of materials; Dielectrics; Flip-chip devices; Materials; Reliability; Stress; Vehicles
• ISBN: 9781467345538; 1467345539
• DOI: 10.1109/EPTC.2012.6507118

Manufacture of highly reliable lead free flip chip devices made in 40nm technology has recently been reported by the authors via the use of large test chips in 42.5×42.5mm body size. These test die were designed to ensure that package die interactions as related to degradation of the dielectric and metal stack used in 40nm silicon technology with lead free bumps could be rigorously evaluated for long term reliability. The work discussed in this paper expands upon the 40nm work to 28nm devices. Additionally, the work was extended to include not only the metal and dielectric stack evaluations but also active transistor and circuit evaluation. This was done to ensure any possible adverse package die interaction effects were captured and addressed via material and process changes. Finally assembled packages were obtained from two different OSATs. The work is summarized in this paper. The data clearly show 28nm active devices assembled with the same processes and bill of materials developed for reliable 40nm large die flip chip packages are robust and reliable.