Power mitigation in high-performance 32-bit MIPS-based CPU on Xilinx FPGAs

• Published in: 2017 IEEE International Conference on Consumer Electronics-Asia (ICCE-Asia) pp. 96 - 101
• Main Authors: Dwivedi, Neha, Chhawcharia, Pradeep
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.10.2017
• Subjects: Clocks; Computer architecture; CPU; Field programmable gate arrays; FPGA; Hardware design languages; HDL modification techniques; ISA; MIPS; ModelSim; Pipelines; Power Reduction; Reduced instruction set computing; Registers; SOC; Verilog
• DOI: 10.1109/ICCE-ASIA.2017.8307850

The purpose of this work is, to introduce design of a 32-bit MIPS (Million Instruction Per Second) based CPU containing five stages of the pipeline, to incorporate power optimization techniques for the processor. The functionality of design is verified by writing Verilog Modules on Xilinx 14.5 choosing the target FPGA device. Synthesis and simulation results have been taken from ModelSim 6.2c. Analysis of the design floorplan of 32-bit CPU and study of the detailed netlist has been achieved on PlanAhead tool, which was giving accurate results. From the performance viewpoint, FPGA-based implementation of processor is totally centered on the designing of processor architectures in Verilog HDL and increasing the overall speedup with power mitigation at Spartan class (45nm and 90nm) FPGAs. The significant features of this work are; increased number of instructions, enhanced performance and low power consumption with HDL modification techniques. The design has consumed less than 119mW of power with the maximum frequency of operation at 70.413MHz for Spartan-6. Optimized power observed was about 22.72% after applying power reduction techniques, which make this work useful for low power FPGAs.