Implementation of a Dynamic Fault-Tolerance Scaling Technique on a Self-Adaptive Hardware Architecture

• Published in: 2009 International Conference on Reconfigurable Computing and FPGAs pp. 445 - 450
• Main Authors: Soto, V.J., Moreno, J.M., Madrenas, J., Cabestany, J.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2009
• Subjects: Biological systems; Biology computing; Computer architecture; dynamic fault tolerance; Energy consumption; Fault detection; Fault tolerance; Field programmable gate arrays; Hardware; Pervasive computing; Routing; self-adaptive; self-configuration; self-placement; self-routing; selforganization
• ISBN: 9781424452934; 1424452937
• ISSN: 2325-6532; 2640-0472
• DOI: 10.1109/ReConFig.2009.45

The purpose of this paper is to describe a dynamic fault tolerance scaling technique that is supported by the self-adaptive features of a hardware architecture developed within the framework of the AETHER project. The architecture is composed of an array of cells that support dynamic and distributed self-routing and self-placement of components in the system. The combination of a large array of cells together with component-level routing ultimately constitutes a SANE (self-adaptive networked entity). The dynamic fault tolerance scaling technique proposed in this paper permits a given subsystem to modify autonomously its structure in order to achieve fault detection and fault recovery. The decision to modify or not its organization is based on the actual power consumption of the system.