Technology roadmaps and low power SoC design

• Published in: 2011 International Electron Devices Meeting pp. 15.4.1 - 15.4.4
• Main Author: Yeric, G.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2011
• Subjects: Benchmark testing; Integrated circuit modeling; Logic gates; Predictive models; Semiconductor process modeling; System-on-a-chip; Transistors
• ISBN: 1457705060; 9781457705069
• ISSN: 0163-1918; 2156-017X
• DOI: 10.1109/IEDM.2011.6131559

Significant change in technology is forecast in the next few process nodes, including the introduction of new transistor structures and increasingly limited interconnect scaling. Technology characteristics drive the planning and optimization of micro-architectures, whose abstracted characteristics are then used to forecast System-on-Chip (SoC) trends in power, performance, and area (PPA). For the coming nodes, extrapolating past trends will not suffice, as entirely new architectures may be better suited to a new technology landscape. This paper will discuss low power design prediction, relating technology roadmap information to circuit metrics, and explore areas for improvement.