A power-efficient reconfigurable two-step VCO-based ADC for software-defined radio

This paper presents the full design flow of a flexible two-step VCO-based Delta-Sigma ADC architecture for software-defined radio applications. The proposed ADC reconfigures its signal bandwidth and A/D conversion accuracy in a cost- and power-efficient method. With the ADC open-loop structure and t...

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Bibliographic Details
Published in2017 IEEE 12th International Conference on ASIC (ASICON) pp. 620 - 623
Main Authors Xinpeng Xing, Peng Zhu, Hui Liu, Wei Wang, Gielen, Georges
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2017
Subjects
3G mobile communication
Bandwidth
Power demand
Quantization (signal)
Transistors
Voltage-controlled oscillators
Wireless LAN
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Summary:This paper presents the full design flow of a flexible two-step VCO-based Delta-Sigma ADC architecture for software-defined radio applications. The proposed ADC reconfigures its signal bandwidth and A/D conversion accuracy in a cost- and power-efficient method. With the ADC open-loop structure and the mostly-digital building blocks, excellent figure-of-merits can be obtained for all modes. A reconfigurable ADC prototype designed in 90nm CMOS technology shows that it achieves 66/80.9dB SNDR respectively within a 20/2MHz signal bandwidth, consuming 5.1/2.9mW of power. The corresponding 78/79.8fJ/step figure-of-merits are among state-of-the-art reconfigurable ADCs, and could be improved even further if technology is scaled.
DOI:10.1109/ASICON.2017.8252552