Embedded decoupling capacitor performance in high speed circuits

• Published in: Proceedings Electronic Components and Technology, 2005. ECTC '05 pp. 1617 - 1622 Vol. 2
• Main Authors: Lixi Wan, Raj, P.M., Balaraman, D., Muthana, P., Bhattacharya, S.K., Varadarajan, M., Abothu, I.R., Swaminathan, M., Tummala, R.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2005
• Subjects: Circuit noise; Costs; Dielectric materials; Frequency; High-K gate dielectrics; Inductance; Packaging; Parasitic capacitance; Surface impedance; Switched capacitor circuits
• ISBN: 0780389077; 9780780389076
• ISSN: 0569-5503; 2377-5726
• DOI: 10.1109/ECTC.2005.1442007

Embedded decoupling is normally considered a better solution than surface mount decoupling for suppressing the switching noise of a high speed digital board/package because of its shorter leads that result in smaller parasitic inductance. This leads to lower impedance over a higher frequency band. It is presumably better in reliability and lowers the cost as well. Designers tend to use large value capacitors for efficient decoupling. Usually, to increase capacitance of an embedded capacitor, one can use a material with higher dielectric constant, design larger electrodes, and reduce the thickness of the dielectric. However, these strategies may sometimes lead to lower performance at high frequency band. This paper will discuss the pros and cons of different embedded capacitor approaches through simulation. As an application example, a typical power/ground network with an embedded capacitor will be compared with that of surface mount discrete capacitor.