Chaos Based Random Clock Generator

• Published in: 2006 49th IEEE International Midwest Symposium on Circuits and Systems Vol. 2; pp. 2 - 6
• Main Authors: Telandro, V., Duval, B., Chaillan, F., Kussener, E.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.08.2006
• Subjects: Chaos; Clocks; CMOS process; CMOS technology; Entropy; Frequency; Oscillators; Signal generators; Temperature; Voltage
• ISBN: 1424401720; 9781424401727
• ISSN: 1548-3746; 1558-3899
• DOI: 10.1109/MWSCAS.2006.382193

The integrated analog system proposed in this paper allows to generate a high entropy random clock signal. It is based on the biasing of an oscillator by a random stair-step current. The step amplitude varies randomly on a continuous, uniformly distributed and width-tunable interval. The step length varies randomly on a continuous interval presenting an average adjustable value. The clock signal thus generated presents frequency jumps between random frequencies, occurring at random instants. Its average frequency is tunable and its frequency variation range is continuous, uniformly distributed and width- adjustable. The proposed implementation uses a chaotic oscillator exhibiting a double-scroll attractor as entropy source. It has been simulated from the process parameters of a STMicroelectronics 0.18 μ m CMOS technology. It consumes less than 1 mW for a frequency variation range centered on 20 MHz and extending symmetrically on 30 MHz. Its characteristics deviation over process, voltage and temperature (PVT) variations is less than 10%. Its estimated area is approximatively 0.01 mm 2 .