A 167-processor 65 nm computational platform with per-processor dynamic supply voltage and dynamic clock frequency scaling
A 167-processor 65 nm computational platform well suited for DSP, communication, and multimedia workloads contains 164 programmable processors with dynamic supply voltage and dynamic clock frequency circuits, three algorithm-specific processors, and three 16 KB shared memories, all clocked by indepe...
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Published in | 2008 IEEE Symposium on VLSI Circuits pp. 22 - 23 |
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Main Authors | , , , , , , , , , , , , , |
Format | Conference Proceeding |
Language | English |
Published |
IEEE
01.06.2008
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Subjects | |
Online Access | Get full text |
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Summary: | A 167-processor 65 nm computational platform well suited for DSP, communication, and multimedia workloads contains 164 programmable processors with dynamic supply voltage and dynamic clock frequency circuits, three algorithm-specific processors, and three 16 KB shared memories, all clocked by independent oscillators and connected by configurable long-distance-capable links. |
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ISBN: | 1424418046 9781424418046 |
ISSN: | 2158-5601 2158-5636 |
DOI: | 10.1109/VLSIC.2008.4585936 |