A 167-processor 65 nm computational platform with per-processor dynamic supply voltage and dynamic clock frequency scaling

A 167-processor 65 nm computational platform well suited for DSP, communication, and multimedia workloads contains 164 programmable processors with dynamic supply voltage and dynamic clock frequency circuits, three algorithm-specific processors, and three 16 KB shared memories, all clocked by indepe...

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Bibliographic Details
Published in2008 IEEE Symposium on VLSI Circuits pp. 22 - 23
Main Authors Truong, D., Cheng, W., Mohsenin, T., Zhiyi Yu, Jacobson, T., Landge, G., Meeuwsen, M., Watnik, C., Mejia, P., Anh Tran, Webb, J., Work, E., Zhibin Xiao, Baas, B.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2008
Subjects
Arrays
Clocks
Digital signal processing
DSP
DVFS
GALS
many-core
Power grids
Program processors
Tiles
Viterbi algorithm
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Summary:A 167-processor 65 nm computational platform well suited for DSP, communication, and multimedia workloads contains 164 programmable processors with dynamic supply voltage and dynamic clock frequency circuits, three algorithm-specific processors, and three 16 KB shared memories, all clocked by independent oscillators and connected by configurable long-distance-capable links.
ISBN:1424418046
9781424418046
ISSN:2158-5601
2158-5636
DOI:10.1109/VLSIC.2008.4585936