A New Direction for III-V FETs for Mobile CPU Operation Including Burst-Mode: In0.35Ga0.65As Channel

• Published in: IEEE electron device letters Vol. 38; no. 3; pp. 314 - 317
• Main Authors: Rakshit, T., Obradovic, B., Wang, W.-E, Kim, W.-H, Shin, K.-M, Baek, S.-C, Lee, S.-W, Kim, S.-H, Lee, J.-M, Kim, D., Hoover, A., Song, W.-B, Cantoro, M., Heo, Y.-C, Rooyackers, R., Ardila, S. C., Vais, A., Lin, D., Collaert, N., Rodder, M. S.
• Format: Journal Article
• Language: English
• Published: IEEE 01.03.2017
• Subjects: Dielectrics; Field effect transistors; high voltage; In₀.₃₅Ga₀.₆₅As; leakage; Logic gates; Mobile communication; mobile CPU; parasitic bipolar effect; Photonic band gap; Silicon; Voltage measurement
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2017.2658447

In this letter, we show that conventional III-V MOSFETs with moderate/high In content channels (In 0.53 Ga 0.47 As or In 0.70 Ga 0.30 As) at scaled nodes are incompatible with mobile SoC designs, which often operate at intermediate/high V dd (0.7 V to ≥1 V) to achieve high frequency including during burst-mode. The incompatibility is due to conventional III-V FETs having too small bandgap, and thus too high leakage when operated at the increased voltages. We show that FETs with a more optimal lower In content, In 0.35 Ga 0.65 As, have the necessary combination of larger bandgap (~Si) and sufficiently high injection velocity (~2.5 times Si) to enable both low leakage and high performance (versus Si), across the entire V dd range of mobile SoC operation. We report for the first time the growth and characterization of ultra-thin In 0.35 Ga 0.65 As FETs with a standard 1nm EOT gate dielectric. Calibrated models show that In 0.35 Ga 0.65 As enables the highest performance at very low leakages at intermediate/high V dd in short channel FETs.