4-Channel Front-End Integrated Circuit For Readout of Large Area of SiPM under Liquid Argon

This paper presents the structure and transistor-level design of CMOS front-end amplifier for the readout of large area SiPM at LAr temperature (87 K). The front-end circuit, a transimpedance amplifier and a summing amplifier, has been designed using a standard 110 nm CMOS technology, and the simula...

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Bibliographic Details
Published in2019 15th Conference on Ph.D Research in Microelectronics and Electronics (PRIME) pp. 201 - 204
Main Author Martinez R., Alejandro D.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.07.2019
Subjects
Capacitance
Cryogenics
Detectors
Gain
Radio frequency
Signal to noise ratio
Transistors
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Summary:This paper presents the structure and transistor-level design of CMOS front-end amplifier for the readout of large area SiPM at LAr temperature (87 K). The front-end circuit, a transimpedance amplifier and a summing amplifier, has been designed using a standard 110 nm CMOS technology, and the simulation results with the foundry PDK are included in this work. Each stage is implemented in a Folded Cascode Operational Transimpedance Amplifier (OTA) architecture with a power rail of +1.25 V and −1.25 V, a power consumption of 95 mW and an open-loop gain over 100 dB. The target sensor is a SiPM tile of 24 cm 2 produced in the Darkside collaboration project, with 6 M of quenching resistance and 6 nF/cm 2 capacitance. For a single photoelectron (250 fC), the front-end can achieve a signal-noise ratio above 12 and a jitter better than 45 ns.
DOI:10.1109/PRIME.2019.8787758