Routability prediction for Field Programmable Gate Arrays with a routing hierarchy

• Published in: 16th International Conference on VLSI Design, 2003. Proceedings pp. 85 - 90
• Main Authors: Zhibin Dai, Banerji, D.K.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2003
• Subjects: Circuits; Electronic mail; Field programmable gate arrays; Logic; Pins; Routing; Switches; Very large scale integration; Wires; Wiring
• ISBN: 0769518680; 9780769518688
• ISSN: 1063-9667; 2380-6923
• DOI: 10.1109/ICVD.2003.1183119

Field Programmable Gate Arrays (FPGAs) have emerged as the key technology for rapidly implementing digital circuits in VLSI. Much research has been done on their architecture and applications. One particularly important area of study is their routing implementation, which is greatly affected by the routing architecture and routing resources. This paper explores the effective utilization of a routing hierarchy that is present in the currently available commercial FPGAs. A stochastic model is adopted to investigate the routability on symmetrical FPGAs containing a routing resource hierarchy. The performance of our model is compared to that of an FPGA without a routing hierarchy. Experimental methods are used to determine the switch consumption of various routing resources. Results show that integrating a routing resource hierarchy into FPGAs causes a design to consume fewer routing resources. Consequently, the speed of designs implemented in such FPGAs can be greatly improved.