Test Pattern Selection and Compaction for Sequential Circuits in an HDL Environment

• Published in: 2010 19th IEEE Asian Test Symposium pp. 53 - 56
• Main Authors: Haghbayan, M H, Karamati, S, Javaheri, F, Navabi, Z
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2010
• Subjects: Circuit faults; Compaction; expectation graph; Hardware design languages; Integrated circuit modeling; PLI; random test generation; sequential circuit; Sequential circuits; shortest sequence; Silicon; Testing
• ISBN: 1424488419; 9781424488414
• ISSN: 1081-7735; 2377-5386
• DOI: 10.1109/ATS.2010.85

In this paper we are revisiting the issue of sequential circuit test generation, and use a selective random pattern test generation method implemented in an HDL environment. The method uses a statistical expectation graph and states of the sequential circuit for selecting the appropriate test vectors to achieve better fault coverage and a more compact test set. To further reduce the size of the generated test set, a static compaction method, which is also implemented in an HDL environment, is used after the test generation process. The experimental results show that selecting good test patterns among random test patterns, not only can be implemented dynamically in an HDL design environment, but also results in a better fault coverage and shorter test pattern length in comparison with some traditional deterministic methods. In addition, it will be shown that static test set compaction methods can considerably reduce the test length of test patterns for sequential designs obtained by our proposed method.