Improving SSD reliability with RAID via Elastic Striping and Anywhere Parity

• Published in: 2013 43rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN) pp. 1 - 12
• Main Authors: Jaeho Kim, Jongmin Lee, Jongmoo Choi, Donghee Lee, Noh, Sam H.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.06.2013
• Subjects: Ash; Bit error rate; Computer architecture; Error correction codes; Flash memory; Microprocessors; RAID; Random access memory; Reliability; SSD
• ISBN: 9781467364713; 1467364711
• ISSN: 1530-0889; 2158-3927
• DOI: 10.1109/DSN.2013.6575359

While the move from SLC to MLC/TLC flash memory technology is increasing SSD capacity at lower cost, it is being done at the cost of sacrificing reliability. An approach to remedy this loss is to employ the RAID architecture with the chips that comprise SSDs. However, using the traditional RAID approach may result in negative effects as the total number of writes may increase due to the parity updates, consequently leading to increased P/E cycles and higher bit error rates. Using a technique that we call Elastic Striping and Anywhere Parity (eSAP), we develop eSAP-RAID, a RAID scheme that significantly reduces parity writes while providing reliability better than RAID-5. We derive performance and lifetime models of SSDs employing RAID-5 and eSAP-RAID that show the benefits of eSAP-RAID. We also implement these schemes in SSDs using DiskSim with SSD Extension and validate the models using realistic workloads. Our results show that eSAP-RAID improves reliability considerably, while limiting its wear. Specifically, the expected lifetime of eSAP-RAID employing SSDs may be as long as current ECC based SSDs, while its reliability level can be maintained at the level of the early stages of current ECC based SSDs throughout its entire lifetime.