Bang-Bang CDR's acquisition, locking, and jitter tolerance

The CDR (Clock and Data Recovery) using PLL with Bang-Bang PD (Phase Detector), CP (Charge Pump), and RC (Resistor and Capacitor) filter is widely used in Serdes circuits. This paper provides a detailed analysis to Bang-Bang CDR's dynamic behaviors and jitter tolerance. Then the slewing conditi...

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Bibliographic Details
Published in2012 25th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE) pp. 1 - 4
Main Authors Chao He, Kwasniewski, T.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.04.2012
Subjects
CDR
Clocks
Detectors
integral path
Integrated circuit modeling
Jitter
jitter tolerance
Phase locked loops
proportional path
slewing
Software packages
Voltage-controlled oscillators
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ISBN1467314315
9781467314312
ISSN0840-7789
DOI10.1109/CCECE.2012.6334824

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Summary:The CDR (Clock and Data Recovery) using PLL with Bang-Bang PD (Phase Detector), CP (Charge Pump), and RC (Resistor and Capacitor) filter is widely used in Serdes circuits. This paper provides a detailed analysis to Bang-Bang CDR's dynamic behaviors and jitter tolerance. Then the slewing conditions, locking condition, and jitter tolerance curve, which are verified by a model implemented in Simulink, are proposed for choosing the filter parameters when designing the circuits.
ISBN:1467314315
9781467314312
ISSN:0840-7789
DOI:10.1109/CCECE.2012.6334824