3D graphics cache system to maximize memory utilization for an embedded system

In this paper, we introduce 3D graphics cache system to increase memory utilization and solve a memory bottleneck problem for an embedded system. We propose a novel pixel cache and a texture cache for a mobile 3D graphics hardware accelerator. The pixel cache enhances rendering performance by adopti...

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Bibliographic Details
Published in2009 International SoC Design Conference (ISOCC) pp. 573 - 576
Main Authors Youngjin Chung, Kilwhan Lee, Jinaeon Lee, Yongsurk Lee
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2009
Subjects
3d graphics
Bandwidth
Degradation
Embedded system
Graphics
Hardware
Interleaved codes
Large scale integration
memory bottleneck
Out of order
pixel cache
SoC
System buses
System-on-a-chip
texture cache multiple outstanding issue
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Summary:In this paper, we introduce 3D graphics cache system to increase memory utilization and solve a memory bottleneck problem for an embedded system. We propose a novel pixel cache and a texture cache for a mobile 3D graphics hardware accelerator. The pixel cache enhances rendering performance by adopting a new write back algorithm and the texture cache also enhances the performance by adopting a multi-level, multi-port and non-blocking architecture. And all caches are optimized for AMBA3.0 AXI on-chip bus protocol. Also the proposed cache architecture can alleviate the memory bottleneck problem by preventing intensive memory accesses and improving cache efficiency by implementing novel cache architectures and multiple outstanding transactions. Also we can reduce a peak power which is a critical problem for an embedded system. We have evaluated the new proposed caches on 3D graphics IP on a SOC environment in where various IPs are embedded. The simulation results show the effectiveness of the proposed methods.
ISBN:9781424450343
1424450349
DOI:10.1109/SOCDC.2009.5423818