Electrostatics improvement in 3-D tri-gate over ultra-thin body planar InGaAs quantum well field effect transistors with high-K gate dielectric and scaled gate-to-drain/gate-to-source separation

• Published in: 2011 International Electron Devices Meeting pp. 33.1.1 - 33.1.4
• Main Authors: Radosavljevic, M., Dewey, G., Basu, D., Boardman, J., Chu-Kung, B., Fastenau, J. M., Kabehie, S., Kavalieros, J., Le, V., Liu, W. K., Lubyshev, D., Metz, M., Millard, K., Mukherjee, N., Pan, L., Pillarisetty, R., Rachmady, W., Shah, U., Then, H. W., Chau, R.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2011
• Subjects: Distance measurement; Electrostatics; FETs; High K dielectric materials; Indium gallium arsenide; Logic gates; Metals
• ISBN: 1457705060; 9781457705069
• ISSN: 0163-1918; 2156-017X
• DOI: 10.1109/IEDM.2011.6131661

In this work, 3-D Tri-gate and ultra-thin body planar InGaAs quantum well field effect transistors (QWFETs) with high-K gate dielectric and scaled gate-to-source/gate-to-drain (L SIDE ) have been fabricated and compared. For the first time, 3-D Tri-gate InGaAs devices demonstrate electrostatics improvement over the ultra-thin (QW thickness, T QW =10nm) body planar InGaAs device due to (i) narrow fin width (W FIN ) of 30nm and (ii) high quality high-K gate dielectric interface on the InGaAs fin. Additionally, the 3-D Tri-gate InGaAs devices in this work achieve the best electrostatics, as evidenced by the steepest SS and the smallest DIBL, ever reported for any high-K III-V field effect transistor. The results in this work show that the 3-D Tri-gate device architecture is an effective way to improve the scalability of III-V FETs for future low power logic applications.