Clock Recovery Gated PLL for Periodically Interrupted and 100% ASK Modulated Signals for a Medical Implant

• Published in: 2017 New Generation of CAS (NGCAS) pp. 97 - 100
• Main Authors: Schutz, Henning, Rothermel, Albrecht, Gambach, Stefan
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.09.2017
• Subjects: Clocks; Implant; Logic gates; Phase frequency detecto; Phase frequency detector; Phase locked loops; Power control; r Amplitude shift keying; RF signals; Voltage-controlled oscillators
• DOI: 10.1109/NGCAS.2017.47

A clock recovery gated phase locked loop (GPLL) for periodically missing input signals and 100% amplitude shift keying modulation is presented. The On-Off keying scheme leads to long periods without an RF signal to extract. This poses special requirements that can be met by using gated PFDs. The power control technique used in this implant periodically shorts the receiving coil, thus limiting the received energy. However, not only does this entail another absence of the RF signal, but it can also lead to a stationary cycle slip, where the VCO performs one cycle too much or less compared to the RF signal. The number of cycle slips can be significantly reduced by implementing two additional PFDs with inverse reset conditions. The proposed PLL with gated PFDs was fabricated and measured in a 350nm high voltage CMOS process. Simulations and performance yield consistent results.