A high speed configurable FPGA architecture for k-mean clustering

This paper presents a high speed configurable FPGA architecture for k-means clustering. The proposed architecture is highly pipelined, parallel and fully configurable. It can achieve an operating frequency of 400 MHz, which is at least three times faster than prior works. The proposed architecture a...

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Bibliographic Details
Published in2013 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 1801 - 1804
Main Authors Kutty, Jithin Sankar Sankaran, Boussaid, Farid, Amira, Abbes
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2013
Subjects
Algorithm design and analysis
Clocks
Clustering algorithms
Computer architecture
Digital signal processing
Field programmable gate arrays
Throughput
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Summary:This paper presents a high speed configurable FPGA architecture for k-means clustering. The proposed architecture is highly pipelined, parallel and fully configurable. It can achieve an operating frequency of 400 MHz, which is at least three times faster than prior works. The proposed architecture addresses the high speed and throughput requirements of machine vision, multi-media and data mining applications.
ISBN:9781467357609
146735760X
ISSN:0271-4302
2158-1525
DOI:10.1109/ISCAS.2013.6572215