Improved Mitchell-based logarithmic multiplier for low-power DSP applications

This paper presents a method to improve the accuracy of a logarithmic multiplier, based on Mitchell's algorithms for calculating logarithms and antilogarithms. The method developed offers an area saving of approximately 50% and a power saving of 71% for larger input widths. A FIR filter based o...

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Bibliographic Details
Published inIEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings pp. 53 - 56
Main Author Mclaren, D.J.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2003
Subjects
Algorithm design and analysis
Clocks
Councils
Design engineering
Digital signal processing
Filters
Interpolation
Power engineering and energy
Signal processing algorithms
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Summary:This paper presents a method to improve the accuracy of a logarithmic multiplier, based on Mitchell's algorithms for calculating logarithms and antilogarithms. The method developed offers an area saving of approximately 50% and a power saving of 71% for larger input widths. A FIR filter based on the multiplier is also presented.
ISBN:0780381823
9780780381827
DOI:10.1109/SOC.2003.1241461