A 10-b 320-MS/s Dual-Residue Pipelined SAR ADC with Binary Search Current Interpolator

This paper presents a 10-bit 320-MS/s dual-residue pipelined SAR ADC. In the proposed ADC, an open-loop gain stage is employed without any calibration by relaxing the offset, gain, and linearity requirements of the inter-stage residue amplifier. Also, a binary search current interpolation is propose...

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Bibliographic Details
Published in2019 IEEE Custom Integrated Circuits Conference (CICC) pp. 1 - 4
Main Authors Cho, Kang-Il, Kwak, Yong-Sik, Kim, Ho-Jin, Boo, Jun-Ho, Lee, Seung-Hoon, Ahn, Gil-Cho
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.04.2019
Subjects
analog-to-digital converter
Capacitors
Computer architecture
dual-residue
Gain
Interpolation
pipeline
Prototypes
Radio access technologies
successive approximation register
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Summary:This paper presents a 10-bit 320-MS/s dual-residue pipelined SAR ADC. In the proposed ADC, an open-loop gain stage is employed without any calibration by relaxing the offset, gain, and linearity requirements of the inter-stage residue amplifier. Also, a binary search current interpolation is proposed for further quantization of the two residue signals. With a gm-cell residue amplifier and two 5-bit current interpolators, the second stage SAR operation is performed using a single comparator. The prototype ADC is fabricated in a 28 nm CMOS process with an active die area of 0.015m m^{2}. Operating at a sampling rate of 320 MHz, the ADC achieves a SNDR and a SFDR of 54.0 dB and 66.4 dB, respectively, at the Nyquist input frequency. It consumes 5.45 mW at a 1.0 V supply voltage, resulting in a Nyquist FoM of 41.6 fJ/conversion-step.
ISSN:2152-3630
DOI:10.1109/CICC.2019.8780117