Fast power network analysis with multiple clock domains

• Published in: 2007 25th International Conference on Computer Design pp. 456 - 463
• Main Authors: Wanping Zhang, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Murgai, R., Shibuya, T., Ito, N., Chung-Kuan Cheng
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.10.2007
• Subjects: Algorithm design and analysis; Clocks; Fitting; Frequency domain analysis; Laplace equations; Noise; Time domain analysis
• ISBN: 9781424412570; 1424412579
• ISSN: 1063-6404; 2576-6996
• DOI: 10.1109/ICCD.2007.4601939

This paper proposes an efficient analysis flow and an algorithm to identify the worst case noise for power networks with multiple clock domains. First, we apply the Laplace transform on the input current sources to derive the analytical formula. Then, we calculate the circuit frequency response with logarithmic scale frequency components. The frequency domain response is approximated by a rational function using vector fitting modeling. The rational function is used to derive the natural frequency of the power ground networks, and can be converted back into time domain easily. Based on the analysis results, we then present the worst case clock gating pattern algorithm to analyze the power networks with multiple clock domains. The most expensive part of the proposed algorithm is the matrix solving: O(F(N) ldr log f ldr D). Function F is the complexity of iterative solution of complex matrix with dimension N. We assume that there are D clock domains and the frequency spans from 0 to f Hz. Experimental results show that our method is up to 60X faster than HSPICE, and can analyze large circuits which are not affordable by HSPICE.