Board level drop impact simulation and test for development of wafer level chip scale package

• Published in: 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC) pp. 1186 - 1194
• Main Authors: Yong Liu, Qiuxiao Qian, Jihwan Kim, Martin, Stephen
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.06.2010
• Subjects: Aluminum; Chip scale packaging; Copper; Damping; Material properties; Polyimides; Semiconductor device modeling; Stacking; Testing; Wafer scale integration
• ISBN: 9781424464104; 1424464102
• ISSN: 0569-5503; 2377-5726
• DOI: 10.1109/ECTC.2010.5490852

In this paper, a comprehensive modeling and test study is presented for the dynamic behaviors of WL-CSP subjected to JEDEC drop impact. A direct non-linear transient implicit dynamic method is introduced with the non-linear dynamic material properties that include solder, the aluminum metal stacking under the UBM and the PCB copper pad. The packages mounted on PCB and under PCB are checked and discussed. The comparison of non-linear dynamic properties for solder, the aluminum metal pad under UBM and the copper pad on PCB is investigated. Then the results for dynamic properties with and without the damping effects are discussed. Then, the dynamic responses of WL-CSP for different polyimide side wall angle, thickness, different UBM geometry and different aluminum pad thickness are investigated and discussed. Finally, the drop test under JEDEC standard has been carried out. The drop test results showed that the corner joints of each corner located WL-CSP at PCB fail first as compared to the chips at other locations. The test results agree with the simulation for the failure modes and the locations.