Single-ended half-swing low-power SRAM design

• Published in: 2008 42nd Asilomar Conference on Signals, Systems and Computers pp. 2108 - 2112
• Main Authors: Choday, H., Stine, J.E.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.10.2008
• Subjects: Capacitance; Circuit simulation; Computer architecture; Inverters; Logic; Power dissipation; Pulse amplifiers; Random access memory; Read-write memory; Voltage
• ISBN: 9781424429400; 1424429404
• ISSN: 1058-6393; 2576-2303
• DOI: 10.1109/ACSSC.2008.5074805

Although memory is a critical component in general-purpose and application-specific processors, it tends to consume a large amount of power. To alleviate this power dissipation, half-swing memory systems have been proposed which allow memory to be accessed with bitlines that do not swing rail to rail. Unfortunately, half-swing memory systems have additional logic to prevent logic from being written or read at the wrong time or with the wrong level. This paper proposes a novel circuit that helps half-swing memory designs to be implemented more efficiently. Moreover, logic is allocated to allow the bitlines to be accessed across one side of a column as opposed to having logic that must access both sides of the memory column. Power results with TSMC SCN6M 0.18 mum technology are explored using repeated circuit simulation and indicate up to 70% savings in total average power dissipation.