Challenges in 3DIC implementation of a design using current CAD tools

• Published in: 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS) pp. 478 - 481
• Main Authors: Neela, G., Draper, J.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.08.2012
• Subjects: Bonding; Clocks; Delay; Design automation; Stacking
• ISBN: 1467325260; 9781467325264
• ISSN: 1548-3746; 1558-3899
• DOI: 10.1109/MWSCAS.2012.6292061

3D chip stacking technology has been gaining traction in recent years, as academia and industry are showing greater interest in going vertical. However, most research so far has been limited to theoretical analysis due to lack of industry-standard CAD tools to design 3D chips. In this paper, a 3DIC implementation of a single precision floating-point unit is discussed with the aim of identifying limitations of the current tools and methodologies. This design is developed by modifying an existing 2D design. The partition criterion is inspired by the architecture of the design, which can take advantage of stacking and enable the use of existing CAD tools. This chip contains two face-to-face bonded tiers. Results show 41.5% reduced chip footprint and 3% increased speed, in spite of the floating-point unit being too small a design to fully exploit the third dimension. The chip is built using the Tezzaron-Global Foundries 130nm process technology package provided by the MOSIS organization.