A low-power vdd-management technique for high-speed domino circuits

A low power voltage management technique is proposed to reduce power consumption for domino circuits. Exploiting a rising and charge-sharing voltage allow the domino circuits to have both high performance and low power consumption. A test chip has been successfully validated to achieve 68% dynamic p...

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Bibliographic Details
Published inProceedings of 2011 International Symposium on VLSI Design, Automation and Test pp. 1 - 4
Main Authors Yu-Tzu Tsai, Hsiang-Hui Huang, Sheng-Wei Hsu, Ching-Hwa Cheng, Jiun-In Guo
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.04.2011
Subjects
Circuit synthesis
Clocks
CMOS integrated circuits
Delay
Design automation
Logic gates
Power demand
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Summary:A low power voltage management technique is proposed to reduce power consumption for domino circuits. Exploiting a rising and charge-sharing voltage allow the domino circuits to have both high performance and low power consumption. A test chip has been successfully validated to achieve 68% dynamic power consumption and 15% static power consumption respectively using TSMC 0.13um CMOS technology.
ISBN:9781424485000
1424485002
DOI:10.1109/VDAT.2011.5783556