FT-EST Framework: Reliability Estimation for the Purposes of Fault-Tolerant System Design Automation

The complexity of today's systems is growing along with the level of chip integration. This results in higher demand for reliability techniques; it also increases the difficulty of incorporating reliability in such systems. For this purpose, we are working on a method to automate reliability in...

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Bibliographic Details
Published in2018 21st Euromicro Conference on Digital System Design (DSD) pp. 244 - 251
Main Authors Lojda, Jakub, Podivinsky, Jakub, Cekan, Ondrej, Panek, Richard, Kotasek, Zdenek
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.08.2018
Subjects
Automation
Circuit faults
Estimation
Fault tolerance
Fault Tolerance Property Estimation
Fault-Tolerant
Field programmable gate arrays
FT-EST
High-Level Synthesis
Redundant Data Type
System analysis and design
Verification
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Summary:The complexity of today's systems is growing along with the level of chip integration. This results in higher demand for reliability techniques; it also increases the difficulty of incorporating reliability in such systems. For this purpose, we are working on a method to automate reliability insertion; however, for this method, it is necessary to have feedback on the result. In this paper, one component of the automation flow enabling the estimation of the resulting reliability - Fault Tolerance ESTimation (FT-EST) framework - is presented along with an improvement for accelerating the time necessary to reach the estimation. For the purpose of evaluation, we are using our Redundant Data Types approach, which enables us to intentionally insert reliability in a particular operation. The estimation utilizes the concept of fault injection. The results indicate, that the concept of Redundant Data Types is functional, however, also suggest its future improvements (e.g. for the operation of subtraction).
DOI:10.1109/DSD.2018.00053