Formal Verification of Power Management Logic with Mixed-Signal Domains

• Published in: 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID) pp. 239 - 244
• Main Authors: Mandal, Sudipa, Da Costa, Antonio Bruto, Hazra, Aritra, Dasgupta, Pallab, Naware, Bhushan, Chunduri, Rama Mohan, Basu, Sanjib
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.01.2017
• Subjects: Clocks; Computer bugs; Fabrics; Phase locked loops; Sequential analysis; Timing; Voltage control
• ISSN: 2380-6923
• DOI: 10.1109/VLSID.2017.43

System on Chip (SoC) designs today have a large number of power domains regulated by complex on-chip power management logic. The power management logic is primarily digital in nature, but it relies on analog components such as Low Dropout Regulators (LDO) and Phase-Locked Loops (PLL) for delivery of regulated voltages and clock frequencies. In low power designs, such analog components may also be powered down at times, and hence power domains are defined around modules containing these components. The digital brain of the power management logic must correctly consider the latencies of the analog components in the power management fabric while switching the power domains driven by these components. This is a task which has become extremely complex by virtue of the multitude of LDOs and PLLs in a modern integrated circuit, and the numerous domains that they drive. This paper presents, for the first time, a formal verification methodology for automatically generating the necessary assertions from an extended syntax of the Unified Power Format (UPF) and proving them on the power management logic using available industrial formal verification tools.