FPGA implementation of wavelet packet transform with reconfigurable tree structure

• Published in: Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics: Inventing the Future Vol. 1; pp. 244 - 251 vol.1
• Main Authors: Trenas, M.A., Lopez, J., Zapata, E.L.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2000
• Subjects: Circuit testing; Computer architecture; Field programmable gate arrays; Filtering; Image coding; Signal processing; Signal resolution; Time frequency analysis; Wavelet packets; Wavelet transforms
• ISBN: 0769507808; 9780769507804
• ISSN: 1089-6503; 2376-9505
• DOI: 10.1109/EURMIC.2000.874639

The wavelet packet transform (WPT) provides good spectral and temporal resolutions in arbitrary regions of the time-frequency plane. This flexible choice of the time-frequency tiling benefits most of the applications where the standard wavelet transform (WT) has already shown to be useful. Examples of these application areas are: signal and image compression, non-linear filtering or denoising, speech coding, medical and biomedical signal and image processing, and communication. However though many specific architectures have been proposed in the literature for the WT it is not the case for WPT. We propose a folded word-serial pipelined architecture able of computing a complete WPT binary tree in an on-line fashion, but easily configurable in order to compute any required WPT subtree. This architecture has been tested by means of a functional simulation and the implementation of its control circuitry on an FPGA device.