Industrial evaluation of DRAM tests

This paper presents the results of 44 well known memory tests applied to 1896 1M*4 DRAM chips, using up to 96 different stress combinations with each test. The results show the importance of selecting the right stress combination, and that the theoretically better tests (i.e. those covering differen...

Full description

Saved in:
Bibliographic Details
Published inDesign, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) pp. 623 - 630
Main Authors van de Goer, A.J., de Neef, J.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1999
Subjects
Computer architecture
Electronic switching systems
Hip
Indium phosphide
Information technology
Leakage current
Postal services
Random access memory
Stress
Testing
Online AccessGet full text

Cover

More Information
Summary:This paper presents the results of 44 well known memory tests applied to 1896 1M*4 DRAM chips, using up to 96 different stress combinations with each test. The results show the importance of selecting the right stress combination, and that the theoretically better tests (i.e. those covering different functional faults) also have a higher fault coverage. However the currently used fault models still leave much to be explained; e.g., the used data backgrounds and address orders show an unexplainable large variation in fault coverage.
ISBN:9780769500782
0769500781
DOI:10.1109/DATE.1999.761194