Robust emulation of shared memory using dynamic quorum-acknowledged broadcasts

The paper presents a robust emulation of multi-writer/multireader registers in message-passing systems using dynamic quorum configurations. In addition to processor and link failures, this emulation tolerates changes in quorum configurations, i.e., on-line replacements of one quorum system consistin...

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Bibliographic Details
Published inProceedings of IEEE 27th International Symposium on Fault Tolerant Computing pp. 272 - 281
Main Authors Lynch, N.A., Shvartsman, A.A.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1997
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Summary:The paper presents a robust emulation of multi-writer/multireader registers in message-passing systems using dynamic quorum configurations. In addition to processor and link failures, this emulation tolerates changes in quorum configurations, i.e., on-line replacements of one quorum system consisting of read and write quorums with another such system. The new emulation is specified using a modular two-layer architecture. The lower layer uses unreliable broadcast to disseminate a client request to a set of processors, and then to collect responses from a subset of the processors. The higher layer emulates robust multi-writer/multi-reader registers where quorum configurations are used to ensure register atomicity. A unique feature of the read/write service is that it implements dynamically changing quorum configurations. The processor designated as the reconfigured executes requests that replace the current configuration with a new configuration. The combination of the higher and lower layers allows essentially unlimited concurrency and does not involve locks. Waiting can occur only due to processor or link failures that disconnect at least one processor in each read quorum or at least one processor in each write quorum of the specified configurations. Additional computation and communication overhead can be incurred by the read and write operations when they encounter frequent reconfigurations. The algorithms are specified here in terms of I/O automata and their correctness is proved using invariants and partial-order methods.
ISBN:9780818678318
0818678313
ISSN:0731-3071
2375-124X
DOI:10.1109/FTCS.1997.614100