An algorithm-hardware-system approach to VLIW multimedia processors

A number of recently published DSPs and multimedia processors emphasize on Very Long Instruction Word (VLIW) architectures to achieve flexibility, processing power and high-level language programmability needed for future multimedia applications. In this paper we show that exclusive exploitation of...

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Bibliographic Details
Published inProceedings of First Signal Processing Society Workshop on Multimedia Signal Processing pp. 433 - 438
Main Authors Kneip, J., Berekovic, M., Pirsch, P.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1997
Subjects
Algorithm design and analysis
Centralized control
Clocks
Communication system control
Control systems
Costs
Multiprocessing systems
Parallel processing
Very large scale integration
VLIW
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Summary:A number of recently published DSPs and multimedia processors emphasize on Very Long Instruction Word (VLIW) architectures to achieve flexibility, processing power and high-level language programmability needed for future multimedia applications. In this paper we show that exclusive exploitation of instruction level parallelism decreases in efficiency as the degree of parallelism increases. This is mainly caused by algorithm characteristics, VLSI design and compiler restrictions. We discuss selected aspects from these fields and possible solutions to upcoming bottlenecks from a practical point of view.
ISBN:9780780337800
0780337808
DOI:10.1109/MMSP.1997.602673