Experiments with the Hi-PASS DSP synthesis system

• Published in: 1992 IEEE International Symposium on Circuits and Systems (ISCAS) Vol. 1; pp. 168 - 171 vol.1
• Main Authors: Duncan, P., Sprouse, S., Potasz, D., Jain, R., Cammack, W., Gafter, N., Wong, Y., Gass, W.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1992
• Subjects: Assembly systems; Code standards; Design automation; Digital signal processing; Finite impulse response filter; Hardware; Parallel architectures; Real time systems; Silicon; Time sharing computer systems
• ISBN: 9780780305939; 0780305930
• DOI: 10.1109/ISCAS.1992.229987

Hi-PASS is a CAD system for synthesizing maximally parallel architectures to implement real-time DSP algorithms. The target DSP applications are the class for which desired sample rates are too high for time sharing of hardware to be feasible. Hi-PASS accepts a C code description of the design to be synthesized and produces a structural description of the final design that can be fabricated using standard cells provided by the Lager IV silicon assembly system. Synthesis experiments carried out with Hi-PASS fall into two categories: application classes where the algorithm can be mapped onto standard functions, such as FIR and IIR filters, for which dedicated functional compilers exist, and applications where the algorithm cannot be mapped to standard functional blocks and which require a genuine architecture synthesis approach with many levels of optimization. Results for FIR filters show that Hi-PASS synthesizes architectures of comparable quality in terms of area and throughput to those generated by a dedicated functional compiler. Results for an edge detection image processing algorithm of the second category show that Hi-PASS provides significant optimization gains.< >