Fault characterisation of complementary pass-transistor logic circuits
Complementary pass-transistor logic (CPL) circuits result in speed improvement and power reduction compared to conventional static CMOS logic. However, the behaviour of this logic family under fault has not yet been studied. This paper presents the results of an investigation into the behaviour of C...
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Published in | 2000 IEEE International Conference on Semiconductor Electronics Proceedings pp. 80 - 84 |
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Main Authors | , , |
Format | Conference Proceeding |
Language | English |
Published |
IEEE
2000
|
Subjects | |
Online Access | Get full text |
ISBN | 9780780364301 0780364309 |
DOI | 10.1109/SMELEC.2000.932438 |
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