Fault characterisation of complementary pass-transistor logic circuits

Complementary pass-transistor logic (CPL) circuits result in speed improvement and power reduction compared to conventional static CMOS logic. However, the behaviour of this logic family under fault has not yet been studied. This paper presents the results of an investigation into the behaviour of C...

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Bibliographic Details
Published in2000 IEEE International Conference on Semiconductor Electronics Proceedings pp. 80 - 84
Main Authors Aziz, S.M., Harun-ur Rashid, A.B.M., Karim, M.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2000
Subjects
Circuit faults
Circuit testing
CMOS logic circuits
Electrical fault detection
Fault detection
Logic circuits
Logic testing
Monitoring
Power engineering and energy
Threshold voltage
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Summary:Complementary pass-transistor logic (CPL) circuits result in speed improvement and power reduction compared to conventional static CMOS logic. However, the behaviour of this logic family under fault has not yet been studied. This paper presents the results of an investigation into the behaviour of CPL circuits under various single faults. It is shown that all single transistor stuck-on faults are only detectable by I/sub DDQ/ testing, while all single stuck-open faults are only detectable by logic monitoring. The majority of the single bridging faults between the gate and source/drain terminals of the MOS transistors can be detected by current monitoring while a few are undetectable.
ISBN:9780780364301
0780364309
DOI:10.1109/SMELEC.2000.932438