The architecture of OCMP and its evaluation

By gathering multiple processors in one LSI chip, communication delay between processors becomes shorter and then efficient fine/medium grain parallel processing can be realized. The authors propose a new processor architecture called OCMP (On-Chip Multi-Processing Architecture). OCMP has two charac...

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Bibliographic Details
Published inProceedings of the 1997 International Symposium on Parallel Architectures, Algorithms and Networks (I-SPAN'97) pp. 71 - 77
Main Authors Saisho, K., Sano, T., Fukuda, A.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1997
Subjects
Costs
Delay
Dispatching
Erbium
Memory management
Multiprocessing systems
Parallel processing
Processor scheduling
Registers
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Summary:By gathering multiple processors in one LSI chip, communication delay between processors becomes shorter and then efficient fine/medium grain parallel processing can be realized. The authors propose a new processor architecture called OCMP (On-Chip Multi-Processing Architecture). OCMP has two characteristics: one is the instruction level dispatching mechanism; and the other is the divided cache system. OCMP employs a fork-join type parallel processing model in order to simplify the dispatching mechanism. By dividing the cache system into shared cache and private cache, the cache coherence problem between processors on the same chip is removed and access conflict on the shared cache is also relaxed. OCMP is evaluated with the instruction level simulator developed by the authors. Two types of instruction level dispatching mechanisms are compared. The memory access mechanism is evaluated with various parameters such as memory access cost, the degree of simultaneous access to shared cache, and so on.
ISBN:0818682596
ISSN:1087-4089
2375-527X
DOI:10.1109/ISPAN.1997.645057