Injector design for optimized tunneling in standard CMOS floating-gate analog memories

Programming mechanisms in floating-gate non-volatile (EEPROM) standard-CMOS memories are briefly reviewed. A methodology to optimize the programming time in poly1-poly2 Fowler-Nordheim based structures is proposed. From design constraints, the optimum number of bumps and bootstrap capacitance value...

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Bibliographic Details
Published in1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268) pp. 426 - 429
Main Authors Madrenas, J., Ivorra, A., Alarcon, E., Moteno, J.M.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1998
Subjects
Adaptive systems
Analog memory
Design optimization
DH-HEMTs
Electrons
EPROM
Flash memory
Nonvolatile memory
Tunneling
Voltage
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Summary:Programming mechanisms in floating-gate non-volatile (EEPROM) standard-CMOS memories are briefly reviewed. A methodology to optimize the programming time in poly1-poly2 Fowler-Nordheim based structures is proposed. From design constraints, the optimum number of bumps and bootstrap capacitance value are obtained to maximize the programming speed for a given programming voltage.
ISBN:9780818689147
0818689145
DOI:10.1109/MWSCAS.1998.759522