Hysteresis tunable FGMOS comparator

• Published in: 2000 IEEE International Conference on Semiconductor Electronics Proceedings pp. 173 - 177
• Main Authors: Nandhasri, K., Ngarmnil, J.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2000
• Subjects: Capacitance; Capacitors; Circuit simulation; CMOS process; Electronic mail; Equations; Hysteresis; MOSFET circuits; Tunable circuits and devices; Voltage control
• ISBN: 9780780364301; 0780364309
• DOI: 10.1109/SMELEC.2000.932458

A novel hysteresis tunable voltage comparator is presented. The circuit is basically a simple voltage comparator embedded with a positive feedback scheme to create the hysteresis. In this work, two floating-gate MOSFETs (FGMOS), are employed to perform the feedback where one of the control gate voltages is used to tune an amount of the feedback current for the input devices. As a result, V/sub TRP+/ and V/sub TRP-/ of the comparator can be tuned electronically. The proposed idea is implementable on standard double-poly CMOS processes. Since the design is normally incorporated with the FGMOS layout in order to get the value of the gate capacitances effectively, Magic Program is used to create the layouts on the AMI 1.2 /spl mu/m CMOS process available through MOSIS. Simulation results from HSPICE are given to demonstrate the functionality.