Memory performance in chip-on-chip packages: Optimizing memory/ASIC integration

Chip-on-chip MCM packaging combines the benefits of conventional MCM methods with conventional ASIC/commercial memory printed circuit board design methods. COC can reduce board space, increase performance, maintain a cost competitive position and offer an alternative to embedded SRAM and DRAM in the...

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Bibliographic Details
Published inProceedings. 1998 IEEE Symposium on IC/Package Design Integration (Cat. No.98CB36211) pp. 16 - 20
Main Authors O'Connor, K.J., Low, Y.L., Gregus, J.A., Degani, Y.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1998
Subjects
Application specific integrated circuits
Assembly
Bonding
Costs
EPROM
Packaging
Random access memory
Space technology
Testing
Very large scale integration
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Summary:Chip-on-chip MCM packaging combines the benefits of conventional MCM methods with conventional ASIC/commercial memory printed circuit board design methods. COC can reduce board space, increase performance, maintain a cost competitive position and offer an alternative to embedded SRAM and DRAM in the appropriate situations. We show that additional testing for known-good-die is minimal, functional to parametric memory yield is very high, COC module assembly is simple and straightforward, and final packaging is essentially identical to conventional ASIC packaging processes.
ISBN:081868433X
9780818684333
DOI:10.1109/IPDI.1998.663614