HDL-based modeling of embedded processor behavior for retargetable compilation
The concept of retargetability enables compiler technology to keep pace with the increasing variety of domain-specific embedded processors. In order to achieve user retargetability, powerful processor modeling formalisms are required. Most of the recent modeling formalisms concentrate on horizontal,...
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Published in | Proceedings. 11th International Symposium on System Synthesis (Cat. No.98EX210) pp. 51 - 54 |
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Main Author | |
Format | Conference Proceeding |
Language | English |
Published |
IEEE
1998
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Subjects | |
Online Access | Get full text |
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Summary: | The concept of retargetability enables compiler technology to keep pace with the increasing variety of domain-specific embedded processors. In order to achieve user retargetability, powerful processor modeling formalisms are required. Most of the recent modeling formalisms concentrate on horizontal, VLIW-like instruction formats. However, for encoded instruction formats with restricted instruction-level parallelism (ILP), a large number of ILP constraints might need to be specified, resulting in less concise processor models. This paper presents an HDL-based approach to processor modeling for retargetable compilation, in which ILP may be implicitly constrained. As a consequence, the formalism allows for concise models also for encoded instruction formats. The practical applicability of the modeling formalism is demonstrated by means of a case study for a complex DSP. |
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ISBN: | 9780818686238 0818686235 |
ISSN: | 1080-1820 |
DOI: | 10.1109/ISSS.1998.730596 |