Experimental evaluation of resonant clock distribution

• Published in: IEEE Computer Society Annual Symposium on VLSI pp. 135 - 140
• Main Authors: Juang-ying Chueh, Ziesler, C.H., Papaefthymiou, M.C.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2004
• Subjects: Capacitance; Clocks; Flip-flops; Frequency; Power generation; Resonance; RLC circuits; Switches; Very large scale integration; Voltage
• ISBN: 0769520979; 9780769520971
• DOI: 10.1109/ISVLSI.2004.1339520

Energy recovery (a.k.a. adiabatic) systems present an attractive alternative to conventional designs due to their significant potential for reducing power. In practical versions of these systems, flip-flops are typically synchronized by a sinusoidal power-clock waveform through a resonant clock distribution network. Understanding clock skew is particularly important in energy recovery systems, because unlike their conventional counterparts, they do not use square clock waveforms or buffers. We have performed an experimental evaluation of clock skew in resonant H-shape clock distribution networks with sinusoidal waveforms. Our results show that compared to conventional clock distribution methodologies in high performance processors, properly designed low-power resonant clocking provides comparable or better skew. Our paper is the first study to suggest a number of practical design guidelines for low-skew resonant clocking, through a systematic investigation of the impact of width, spacing, and loading of the clock tree on clock skew.