Modeling of realistic on-chip power grid using the FDTD method

• Published in: 2002 IEEE International Symposium on Electromagnetic Compatibility Vol. 1; pp. 238 - 243 vol.1
• Main Authors: Jinseong Choi, Lixi Wan, Swaminathan, M., Beker, B., Master, R.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2002
• Subjects: Capacitors; Computational modeling; Delay; Finite difference methods; Kirchhoff's Law; Network-on-a-chip; Power grids; Power systems; SPICE; Time domain analysis
• ISBN: 0780372646; 9780780372641
• DOI: 10.1109/ISEMC.2002.1032481

In this paper, a multi-layered on-chip power distribution network has been modeled using the finite difference time domain (FDTD) method. This simulation consists of 0.5 million passive elements, 40000 distributed current sources and multiple C4 vias. In this method, a branch capacitor has been used, which is different from latency insertion method (LIM). The use of the branch capacitor is important for simulating multi-layered power grids. The current in the branch capacitor is extracted from Kirchhoffs current law. This provides a good model of the branch capacitor and does not require companion models during simulation. The proposed model has been verified with SPICE through a simple example. The on-chip power grid simulation, the characteristics of noise propagation and the effectiveness of on-chip decoupling capacitors have been discussed. Also the importance of the nonlinearity in the computation of the power supply noise in on- chip power grid has been addressed through the peak noise analysis using linear current source and clock distribution network.