Towards an artificial neural network framework

• Published in: Proceedings 2002 NASA/DoD Conference on Evolvable Hardware pp. 266 - 273
• Main Authors: Schurmann, F., Hohmann, S., Schemmel, J., Meier, K.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2002
• Subjects: Application specific integrated circuits; Artificial neural networks; Digital circuits; Field programmable gate arrays; Network topology; Neural network hardware; Neural networks; Neurons; Scalability; Signal processing
• ISBN: 0769517188; 9780769517186
• DOI: 10.1109/EH.2002.1029893

This paper proposes a framework for hardware artificial neural networks (ANN) combining scalability with the flexibility of software solutions and the speed of hardware ANNs. Our implementation consists of analog neural network blocks realized as ASICs configurable to form arbitrary and large networks having simple elementary resources, i.e. synapses and neurons. Scalability is assured by confining the analog processing of the synapses to blocks and using digital signalling between them. With the help of a genetic algorithm we train the network to combine its elementary resources to form variable network building blocks. We demonstrate how three binary input neurons can act as a single 3-bit neuron and how a group of neurons and synapses can be trained to form a 3-bit output neuron with linear and sigmoid activation functions.