A low power sample-and-hold amplifier
A novel power reduction technique is proposed for a sample-and-hold amplifier (SHA) with two stage operational amplifier. This technique improves the bandwidth and the slew rate of the SHA can be reduced. A variable gain amplifier (VGA) used in an analog-digital interface system for mega-pixel CCD i...
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Published in | ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705) pp. 477 - 480 |
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Main Authors | , , , , , |
Format | Conference Proceeding |
Language | English |
Published |
IEEE
2003
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Subjects | |
Online Access | Get full text |
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Summary: | A novel power reduction technique is proposed for a sample-and-hold amplifier (SHA) with two stage operational amplifier. This technique improves the bandwidth and the slew rate of the SHA can be reduced. A variable gain amplifier (VGA) used in an analog-digital interface system for mega-pixel CCD image sensors is implemented. Fabricated in 0.25-/spl mu/m CMOS process with MIM capacitors, the VGA occupies 0.49 /spl times/ 0.49 mm/sup 2/ and dissipates 18.7 mW at 18 MHz with a supply voltage of 3.1 V. |
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ISBN: | 0780379950 9780780379954 |
DOI: | 10.1109/ESSCIRC.2003.1257176 |